Shashank Kumar

Education

2023–2027

B.Tech, Electronics & Communication Engineering

National Institute of Technology, Tiruchirappalli

Expected graduation in 2027.

2022

Higher Secondary Education

St. Teresa's College, Lucknow, Uttar Pradesh

2020

Secondary Education

St. Teresa's College, Lucknow, Uttar Pradesh

Interests

A few things I enjoy in my free time.

Low Level Computing

Also interested in low-level programming and understanding how hardware and software interact at the most fundamental level.

Travelling

Fond of exploring new places, experiencing different surroundings, and getting away from the usual routine.

Books

I enjoy reading books on a variety of topics, from science and technology to mystery and philosophy.

Experience

May–Jun 2025

Research Intern

National Institute of Technology, Tiruchirappalli

Contributed to the FPGA implementation of a 1D CNN-based ECG signal classification system, designing systolic-array multipliers and a MAC unit in Verilog for efficient convolution. Performed RTL-level functional verification of pipelined arithmetic datapaths and control logic through simulation.

May–Jul 2026

SURGE Intern

Indian Institute of Technology Kanpur

Designed and simulated a Class-B RF power amplifier using a 65 nm CMOS PDK, developing an adaptive feedforward bias technique with replica biasing to reduce crossover distortion while maintaining efficiency. Designed and simulated the layout of an on-chip transformer by modifying a PDK inductor.

Projects

Jun 2026

Design and Verilog Implementation of a RISC-V Core using RV32I ISA

Designed and implemented a basic RISC-V processor in Verilog based on the RV32I open-source instruction set architecture. Architected the instruction decoder to classify R, I, S, B, U, and J-type instructions and generate control signals for datapath execution. Verified functional correctness through simulation using custom instruction sequences to validate instruction flow and pipeline behaviour.

Aug 2025 – Feb 2026

FPGA Based Maze Solving Bot — E-Yantra Initiative

Worked on developing an autonomous maze-solving robot on FPGA using Verilog and the Trémaux algorithm to compute an optimal navigation path from real-time ultrasonic and IR sensor inputs. Designed a custom UART interface for Bluetooth communication, integrated ultrasonic, DHT, and soil-moisture sensors, and implemented PWM-based motor control entirely in Verilog. Verified RTL functionality through simulation and on-board FPGA debugging.

Jun 2025

Asynchronous FIFO Design in Verilog with Dual Clock Domains and Synchronizer

Designed and implemented a parameterized asynchronous FIFO in Verilog for safe data transfer between independent clock domains. Used Gray-coded read/write pointers and double flip-flop synchronizers to mitigate metastability and ensure reliable clock-domain crossing, with robust full and empty flag logic to manage FIFO status.

Manager Aug 2025 – Aug 2026

Delta Force

The Official Programming Club of NIT Tiruchirappalli

Worked across student-facing platforms and event initiatives, collaborating with teams to deliver reliable web experiences for the campus community.

Dashboard Management Team

Worked on revamping the institute’s official dashboard used by students for mess registration, improving the experience of a key campus service.

Festember WebOps Team

Contributed to developing room-booking and payment portals for Festember, NIT Trichy’s official cultural festival.

Team Terrabound - A Pragyan Initiative

Contributed to developing Terrabound, a tactical game initiative that engaged 200+ players.